PCIE GEN4 PHY IP
l Support 16GT 8GT 5GT 2.5GT data rate
l Compliant with PCI Express 4.0, 3.1, 2.1, 1.1 and PIPE 4.2 standards
l x1, x2, x4, x8, x16 lane configuration with bifurcation
l Multi-tap adaptive programmable continuous time linear equalizer
(CTLE) and decision feedback equalizer (DFE)
l Support L1 SUB low power consumption mode status
l Support SRIS
l Built-in self-check vector, PRBS generation and check mechanism
l Temperature range -40℃-125℃
l Support Flip chip packaging