In January 2020, Chengdu Naneng Microelectronics released a multi-protocol General Video Interface (GVI) physical layer PHY IP core for SOC/ASIC chips. GVI PHY IP is specifically designed for smart TVs, projection equipment, and monitoring chips. Multi-channel multi-protocol video transmission PHY IP core designed for, monitors and other types of high-definition video display chips, which can meet the electrical characteristics and transmission data rate requirements of mainstream video interface protocols such as eDP, MIPI, and is backward compatible with traditional LVDS video Transmission technology. The compatibility of the GVI interface, low power consumption, small area, and arbitrarily configurable number of channels provide video SOC customers with great convenience and flexibility in choosing interface IP cores.
As the mainstream transmission protocol for video pixels, LVDS technology has been widely used in TVs, tablets, notebook computers and devices with built-in LCD displays. With the application growth of high-definition pictures, that is, the continuous improvement of display resolution, LVDS has been unable to meet the needs of high bandwidth and low power consumption, and has become an outdated interface. On this basis, MIPI, DP/eDP and other video interface technologies have become the mainstream, and Naneng Energy Micro GVI IP core has emerged as the times require, completing the universal compatibility of the electrical characteristics of these video technologies, giving customers the opportunity to use SOC chips It is convenient to use different video interfaces and switch freely.
MIPI stands for Mobile Industry Processor Interface (Mobile Industry Processor Interface). It is an open standard and a specification for mobile application processors initiated by the MIPI Alliance. MIPI defines a set of interface standards to standardize the internal interfaces of mobile devices such as cameras, displays, basebands, and radio frequency interfaces, thereby increasing design flexibility while reducing cost, design complexity, power consumption and EMI.
eDP is an internal digital interface based on the DisplayPort architecture and protocol. While supporting the transmission of high-definition video signals, it also adds the transmission of high-definition audio signals, and supports higher resolution and refresh rate. It is suitable for tablet computers, notebooks, all-in-ones, and future new large-screen high-resolution mobile phones.
The GVI PHY IP core released by Naneng Micro can meet the above-mentioned multiple video signal serial communication standards at the interface electrical characteristics level, so that customers with video interface design requirements SOC/ASIC can flexibly use various next-generation high-speed video interface protocols You can switch between them and enjoy the advantages of GVI IP’s ultra-low power consumption and small area in chip design. At the same time, it can also be compatible with the inherent LVDS transmission mode in specific application scenarios.
Naneng micro has currently launched GVI IP at 28nm, 22nm and 40nm nodes in multiple foundries and completed silicon verification and mass production for multiple customers. The maximum channel integration has reached the level of 24 lanes.
USB3.1/3.0 typeC PHY, PCIE Gen3 PHY, SATA Gen3 PHY Mass Production in 55nm Successfully
June 2018，Naneng micro offered a total IP solution to a major storage/SSD IC company in china and together completed a USB3.1 typeC + PCIE Gen3 SSD controller IC with this customer. The SOC chip is using Naneng’s USB3.1/3.0 typeC PHY, USB2.0 PHY, PCIE Gen3 PHY, SATA Gen3 PHY, 5V-12.V DC-DC, 3.3V-1.2V LDO， and 300M OSC with low temp drift. Currently the SOC chip has passed ESD testing, reliability testing and burn-in test, also it passed USB/SATA/PCIE compliance testing with more than 90 mainboards, hard drive/SSD drive and other auxiliary devices.
This SOC chip has moved into mass production on June 2018.
Cadence Asia Management Visited Naneng Micro
On 22nd Dec 2017, Mr. Michael Shih, president of Cadence (Asia Pacific) and his fellow colleagues , visited Naneng micro and investigated the IP portfolio as well as the technology capability of naneng engineering team. Cadence is the one of the largest EDA, IP and designer server solution provider all over the world. During his visit, President Shih explored the potential opportunity w.r.t IP development corporation with Naneng.
GVI PHY IP Move to Mass Production
June 2017, a GVI PHY IP was delivered from naneng micro to one of the biggest SOC company in china and move to mass production. With a wide data rate range from 500Mbps to 4Gbps, this IP full compiles with General Video Interface HS specification, and it is specially designed to cater for 6000V ESD scenario, both IEC and HBM.
GVI PHY IP was adopted in a smartTV controller SOC and generated million pieces production record.
MIE Fujitsu Visited Naneng Micro
22nd Apr, 2017, Mr. Toyama Koki, the director of MIE Fujitsu Semiconductor, as well as his fellow colleagues, visited Naneng Micro.
MIE Fujitsu Semiconductor Limited is a semiconductor foundry company with over thirty years of manufacturing experience. MIE Fujitsu provide customer value add services including ultra-low power consumption, non-volatile memory that is researched and developed in our 300 mm wafer fab in MIE, Japan. Using 40 to 90 nm process technologies, MIE Fujitsu Semiconductor manufactures and mass-produces products with a high level of quality control.
During their visit, the guests from MIE Fujitsu has reviewed IP portfolio and technology capability of Naneng micro, and discussed the potential opportunity of analog/interface IP development.
USB3.1 PHY IP Passed USB Electrical Compliance Test
March 2017, Naneng Micro announced a USB3.1 PHY IP has passed USB electrical compliance test. It is a PHY IP comply with USB 3.1 Gen2 specification, work up to 10Gbps, with Gen1 5Gbps compatibility, this IP can be used directly to support Type-C application. This IP was adopted by a listed company in Taiwan and already move to mass production.
JESD204B PHY IP Move to Production
Oct, 2016, Naneng micro completed a 2 lane flip-chip JESD204 PHY IP core in 65nm node, with 10Gbps per-lane data rate, this IP can reach maximum 20Gbps total bandwidth, and can be used to support ADC/DAC modules for different applications.
This IP fully support all JESD204B features including deterministic latency. It’s been moved to mass production in customer SOC product.
Enlisted in Tianfu (Sichuan) United Share Trading Center
Feb, 2017, Naneng Micro was enlisted in Tianfu (Sichuan) United Share Trading Center (TUSTC), Approved and funded by Sichuan/Tibet provincial governments, and also mainly targeted at both provinces, TUSTC is a one of the major regional share trading platform in china. The main goal of TUSTC is to serve start-up, small and medium sized enterprises for offering a share trading and fund raise platform before these enterprises move to IPO.