Oct, 2016, Naneng micro completed a 2 lane flip-chip JESD204 PHY IP core in 65nm node, with 10Gbps per-lane data rate, this IP can reach maximum 20Gbps total bandwidth, and can be used to support ADC/DAC modules for different applications.
This IP fully support all JESD204B features including deterministic latency. It’s been moved to mass production in customer SOC product.
