Recently, the Sichuan Provincial Private Office released the “Goose Array Cultivation 2021 List”. The first batch of high-tech zones to enter the “Goose Array Cultivation Program” included 15 companies including Naneng Micro, Mike Biology, and Hongqi Chain. The Goose Array Cultivation Plan aims to cultivate enterprises to focus on capital, technology, market and other fields, establish a modern enterprise system, and improve enterprises by promoting development and growth, guiding listing, strengthening factor guarantees, implementing fiscal and taxation policies, consolidating talent support, and improving the service system. Organizational structure and management system; promote the transformation of corporate property rights structure to diversification, shareholding, and securitization; actively support the cultivation of enterprises to enjoy preferential tax policies such as the development of the western region, additional deductions for research and development expenses, and high-tech enterprise technology income tax; encourage the cultivation of enterprises to increase Introduce intelligence; strengthen the guidance and service of enterprise investment and financing, intellectual property, legal affairs, human resources, etc., to promote enterprise reform and development, and accelerate growth. The Goose Array Cultivation Plan strives to spend 5 years to form a geese enterprise group of “leading leading enterprises + superior backbone enterprises + fast-growing enterprises” through classified policies and active cultivation, and achieve the goal of “breaking zero and doubling the increment” of private enterprises in the province.
December 30, 2020 Naneng Micro won the honorary title of “Gazelle Enterprise in Sichuan Province” After review by the expert group of Sichuan Provincial Department of Science and Technology, Naneng Micro was rated as “Gazelle Enterprise in Sichuan Province”. This is the first time that Naneng Micro has received this honor. Since its establishment, Naneng Micro has always maintained its original intention and is committed to providing alternative solutions for independent IP options for the domestic chip industry. In the future, Naneng Micro will continue to work hard to build a large-scale one-stop IP design and service platform in China.
From December 10th to 11th, 2020, the 2020 China Integrated Circuit Design Industry Conference and Chongqing Integrated Circuit Industry Innovation and Development Summit Forum (ICCAD 2020) was successfully held at Chongqing Yuelai International Conference Center. In this “grand event” of the integrated circuit industry, Wu Zhaolei, director of Naneng Micro’s electronic R&D department, delivered a keynote speech on “Advanced Process High-speed Integrated Circuit ESD Design Engineering Realization”. Summarized Nanomicro’s experience in high-speed interface IP ESD design, and explained the ESD phenomenon under advanced technology and the realization of ESD design engineering to the guests present, which was highly recognized by relevant experts.
Cum Chongqing IC Industry Innovation and Development Summit Forum
On December 10-11, 2020, the 2020 China Integrated Circuit Design Industry Conference and Chongqing Integrated Circuit Industry Innovation and Development Summit Forum (ICCAD 2020) will be held in Chongqing, the “city of mountains and rivers”.
Naneng Micro is committed to “being trustworthy IP” and concentrates on providing customers with customized IP services. At Booth 064 of Hall S2 of Chongqing International Expo Center, Nanopower sincerely invites you to gather at this grand event of the integrated circuit industry and look forward to seeing you again.
Time: December 10-11, 2020 Location: Chongqing Yuelai International Convention Center, Chongqing International Expo Center Hall S2 Booth number: 064
Naneng Micro will share with you
IP customized service plan USB, PCIE, SATA PHY and 10G/12.5G SERDES IP solutions under advanced process technology Keynote speech: Speech Forum: Special Forum (3), Huanyue Hall C, 1st Floor, Chongqing Yuelai International Conference Center, 13:10 pm on December 11 Speech topic: Implementation of ESD design engineering for advanced process high-speed integrated circuits Speaker: Wu Zhaolei (Director of R&D Department, Naneng Micro)
On October 28, 2020, Naneng Micro participated in the second Samsung Semiconductor SAFE online exhibition and conducted an online exhibition of Naneng Micro’s IP products.
SAFE exhibition is the ecosystem conference of Samsung FAB, and it is the communication channel and bridge between Samsung FAB customers and suppliers. The SAFE conference gives IP suppliers, EDA companies, packaging manufacturers and other service providers an opportunity to directly communicate with customers, understand customer needs and introduce their products. Due to the impact of the epidemic, this exhibition will be conducted online.
As an IP partner of Samsung FAB, Naneng Micro showcased the company’s PCIE, USB, SATA, MIPI, JESD204B and other high-speed interface IP cores at the exhibition on the 28th, and communicated with potential Samsung customers.
The main focus of this exhibition is Samsung’s advanced technology such as 8nm FINFET and other high-performance computing, automotive electronics, IOT, mobile communications and 5G products.
In November 2020, Naneng Micro organized a two-day Songpinggou group building activity. The Naneng family went to the western Sichuan region to enjoy a different kind of scenery. The red leaves competed with each other, so that the Naneng people who lived in the city for a long time could experience the best nature. Brilliant colors.
The purpose of this team building is to let every Neng Neng employee relax and sharpen his will, hoping to face work and life with a fuller spirit in the future and become a better person.
Naneng Micro was awarded the honorary title of “Gazelle Enterprise” by Chengdu High-tech Zone in September 2020.
“Gazelle Enterprise” is an honorary title established by Chengdu High-tech Development Zone to encourage enterprises with strong innovation vitality and rapid development in the zone. It is reported that in addition to obtaining policy support for venture capital and credit financing, being selected as a “Gazelle Enterprise” can also open up markets for enterprises, participate in major national or local construction projects, government procurement and enterprise independent innovation project declaration, high-tech enterprise identification, R&D investment subsidies and other aspects have received key support from the development zone. The approval to become a member of the “Gazelle Enterprise” of Chengdu High-tech Zone means that Chengdu Naneng Microelectronics’ comprehensive strength and development potential have been highly recognized by the government. This will promote Naneng energy to further expand the market, improve independent innovation capabilities, and strive to become a leader in domestically produced independent controllable integrated circuit IP core technology.
In January 2020, Chengdu Naneng Microelectronics released a multi-protocol General Video Interface (GVI) physical layer PHY IP core for SOC/ASIC chips. GVI PHY IP is specifically designed for smart TVs, projection equipment, and monitoring chips. Multi-channel multi-protocol video transmission PHY IP core designed for, monitors and other types of high-definition video display chips, which can meet the electrical characteristics and transmission data rate requirements of mainstream video interface protocols such as eDP, MIPI, and is backward compatible with traditional LVDS video Transmission technology. The compatibility of the GVI interface, low power consumption, small area, and arbitrarily configurable number of channels provide video SOC customers with great convenience and flexibility in choosing interface IP cores. As the mainstream transmission protocol for video pixels, LVDS technology has been widely used in TVs, tablets, notebook computers and devices with built-in LCD displays. With the application growth of high-definition pictures, that is, the continuous improvement of display resolution, LVDS has been unable to meet the needs of high bandwidth and low power consumption, and has become an outdated interface. On this basis, MIPI, DP/eDP and other video interface technologies have become the mainstream, and Naneng Energy Micro GVI IP core has emerged as the times require, completing the universal compatibility of the electrical characteristics of these video technologies, giving customers the opportunity to use SOC chips It is convenient to use different video interfaces and switch freely. MIPI stands for Mobile Industry Processor Interface (Mobile Industry Processor Interface). It is an open standard and a specification for mobile application processors initiated by the MIPI Alliance. MIPI defines a set of interface standards to standardize the internal interfaces of mobile devices such as cameras, displays, basebands, and radio frequency interfaces, thereby increasing design flexibility while reducing cost, design complexity, power consumption and EMI. eDP is an internal digital interface based on the DisplayPort architecture and protocol. While supporting the transmission of high-definition video signals, it also adds the transmission of high-definition audio signals, and supports higher resolution and refresh rate. It is suitable for tablet computers, notebooks, all-in-ones, and future new large-screen high-resolution mobile phones. The GVI PHY IP core released by Naneng Micro can meet the above-mentioned multiple video signal serial communication standards at the interface electrical characteristics level, so that customers with video interface design requirements SOC/ASIC can flexibly use various next-generation high-speed video interface protocols You can switch between them and enjoy the advantages of GVI IP’s ultra-low power consumption and small area in chip design. At the same time, it can also be compatible with the inherent LVDS transmission mode in specific application scenarios. Naneng micro has currently launched GVI IP at 28nm, 22nm and 40nm nodes in multiple foundries and completed silicon verification and mass production for multiple customers. The maximum channel integration has reached the level of 24 lanes.