Naneng Micro launches multi-protocol universal video interface physical layer IP core —GVI

In January 2020, Chengdu Naneng Microelectronics released a multi-protocol General Video Interface (GVI) physical layer PHY IP core for SOC/ASIC chips. GVI PHY IP is specifically designed for smart TVs, projection equipment, and monitoring chips. Multi-channel multi-protocol video transmission PHY IP core designed for, monitors and other types of high-definition video display chips, which can meet the electrical characteristics and transmission data rate requirements of mainstream video interface protocols such as eDP, MIPI, and is backward compatible with traditional LVDS video Transmission technology. The compatibility of the GVI interface, low power consumption, small area, and arbitrarily configurable number of channels provide video SOC customers with great convenience and flexibility in choosing interface IP cores.
As the mainstream transmission protocol for video pixels, LVDS technology has been widely used in TVs, tablets, notebook computers and devices with built-in LCD displays. With the application growth of high-definition pictures, that is, the continuous improvement of display resolution, LVDS has been unable to meet the needs of high bandwidth and low power consumption, and has become an outdated interface. On this basis, MIPI, DP/eDP and other video interface technologies have become the mainstream, and Naneng Energy Micro GVI IP core has emerged as the times require, completing the universal compatibility of the electrical characteristics of these video technologies, giving customers the opportunity to use SOC chips It is convenient to use different video interfaces and switch freely.
MIPI stands for Mobile Industry Processor Interface (Mobile Industry Processor Interface). It is an open standard and a specification for mobile application processors initiated by the MIPI Alliance. MIPI defines a set of interface standards to standardize the internal interfaces of mobile devices such as cameras, displays, basebands, and radio frequency interfaces, thereby increasing design flexibility while reducing cost, design complexity, power consumption and EMI.
eDP is an internal digital interface based on the DisplayPort architecture and protocol. While supporting the transmission of high-definition video signals, it also adds the transmission of high-definition audio signals, and supports higher resolution and refresh rate. It is suitable for tablet computers, notebooks, all-in-ones, and future new large-screen high-resolution mobile phones.
The GVI PHY IP core released by Naneng Micro can meet the above-mentioned multiple video signal serial communication standards at the interface electrical characteristics level, so that customers with video interface design requirements SOC/ASIC can flexibly use various next-generation high-speed video interface protocols You can switch between them and enjoy the advantages of GVI IP’s ultra-low power consumption and small area in chip design. At the same time, it can also be compatible with the inherent LVDS transmission mode in specific application scenarios.
Naneng micro has currently launched GVI IP at 28nm, 22nm and 40nm nodes in multiple foundries and completed silicon verification and mass production for multiple customers. The maximum channel integration has reached the level of 24 lanes.